1. Field of the Invention
The present invention is concerned with a multi-stage driving circuit for a high capacitive load utilizing five or more intermediate driver circuits cascaded between a signal driver and a load driver. More particularly, the invention is concerned with such a multi-stage driving circuit wherein the total delay of the signal source caused by great disparity between the capacitance of the signal driver circuit and the load driver circuit is minimized.
2. Description of the Prior Art
Most large scale integration circuit chips, whether logic or memory oriented, requires some driving capability, such as for handling long interconnection lines or enabling information display from the chip. The driving circuits for such purposes usually have a specified current handling capacity which is substantially larger than the current handling capacity for similar circuitry in the large scale integration circuits which handle logic functions or storage functions. Accordingly, the off-chip driving circuits comprise devices which are substantially larger in size than the logic function and storage function devices.
However, in design of the chip layout it should be apparent that the logic function and storage function devices are utilized to drive the larger off chip driving circuits. Accordingly, if the disparity between device sizes and current handling capabilities of the devices is very large, excessive delay occurs between the signal driver circuit and the off-chip or load driver circuit. This typically occurs where off-chip driver circuits are utilized to drive high capacitive loads wherein the output capacitance of the off-chip driver circuit is at least one hundred times greater in magnitude than the output capacitance of the on-chip signal driver circuit utilized to drive the former.
The foregoing problem has been widely recognized and some efforts have been made in the past to optimize circuit design to provide minimum propagation delay in the output stages of integrated or large scale integrated circuits. For example, an article titled "An Optimized Output Stage for MOS Integrated Circuits", IEEE Journal of Solid State Circuits, Volume SC10, No. 2, April, 1975 by Lin and Linholm described an output device for optimizing propogation delay and minimizing chip area. According to Lin and Linholm propogation delay may be minimized by means of tapering the size of the output stages of an MOS integrated amplifier whereby a compromise is attained between decreasing propagation delay and increasing the chip area utilized by the cascaded MOS stages.
In addition, other designers have recognized that the delay between a large current capacity, high capacitance output stage and a low current capacity, low capacitance input stage can be minimized by cascading two or more intermediate driver circuits between the stages, each having a capacitance and size falling somewhat between the extremes of the input and output stages. Typically, this type of design has been accomplished by cut and try methods wherein the number of intermediate stages added for minimizing delay comprises a number less than five. Typically these efforts have also involved circuits wherein the capacitance of the output or off-chip driver stage was less than one hundred times that of the signal driver stage. Due to their empirical nature of the circuit design techniques described hereinbefore as utilized in the prior art are generally unsuitable for design of amplifiers having a large number of stages.